Applied. Thanks! Alex
On Mon, Apr 7, 2025 at 1:52 AM Alexandre Demers <[email protected]> wrote: > > The defines, shifts and masks are already available in dce_6_0_d.h, > dce_6_0_sh_mask.h. > > Signed-off-by: Alexandre Demers <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/si.c | 26 +++++++++++++------------- > drivers/gpu/drm/amd/amdgpu/sid.h | 16 ---------------- > 2 files changed, 13 insertions(+), 29 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c > index 3b8c65a966b9..c21f97d89cbe 100644 > --- a/drivers/gpu/drm/amd/amdgpu/si.c > +++ b/drivers/gpu/drm/amd/amdgpu/si.c > @@ -1278,24 +1278,24 @@ static bool si_read_disabled_bios(struct > amdgpu_device *adev) > u32 rom_cntl; > bool r; > > - bus_cntl = RREG32(R600_BUS_CNTL); > + bus_cntl = RREG32(mmBUS_CNTL); > if (adev->mode_info.num_crtc) { > - d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); > - d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); > + d1vga_control = RREG32(mmD1VGA_CONTROL); > + d2vga_control = RREG32(mmD2VGA_CONTROL); > vga_render_control = RREG32(mmVGA_RENDER_CONTROL); > } > rom_cntl = RREG32(R600_ROM_CNTL); > > /* enable the rom */ > - WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); > + WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); > if (adev->mode_info.num_crtc) { > /* Disable VGA mode */ > - WREG32(AVIVO_D1VGA_CONTROL, > - (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | > - AVIVO_DVGA_CONTROL_TIMING_SELECT))); > - WREG32(AVIVO_D2VGA_CONTROL, > - (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | > - AVIVO_DVGA_CONTROL_TIMING_SELECT))); > + WREG32(mmD1VGA_CONTROL, > + (d1vga_control & > ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | > + > D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); > + WREG32(mmD2VGA_CONTROL, > + (d2vga_control & > ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | > + > D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); > WREG32(mmVGA_RENDER_CONTROL, > (vga_render_control & > ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); > } > @@ -1304,10 +1304,10 @@ static bool si_read_disabled_bios(struct > amdgpu_device *adev) > r = amdgpu_read_bios(adev); > > /* restore regs */ > - WREG32(R600_BUS_CNTL, bus_cntl); > + WREG32(mmBUS_CNTL, bus_cntl); > if (adev->mode_info.num_crtc) { > - WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); > - WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); > + WREG32(mmD1VGA_CONTROL, d1vga_control); > + WREG32(mmD2VGA_CONTROL, d2vga_control); > WREG32(mmVGA_RENDER_CONTROL, vga_render_control); > } > WREG32(R600_ROM_CNTL, rom_cntl); > diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h > b/drivers/gpu/drm/amd/amdgpu/sid.h > index 19889276d677..99f6dfae9b81 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sid.h > +++ b/drivers/gpu/drm/amd/amdgpu/sid.h > @@ -81,11 +81,6 @@ > #define MC_CG_ENABLE (1 << 18) > #define MC_LS_ENABLE (1 << 19) > > -#define MC_SHARED_CHMAP 0x801 > -#define NOOFCHAN_SHIFT 12 > -#define NOOFCHAN_MASK > 0x0000f000 > -#define MC_SHARED_CHREMAP 0x802 > - > #define MC_VM_FB_LOCATION 0x809 > #define MC_VM_AGP_TOP 0x80A > #define MC_VM_AGP_BOT 0x80B > @@ -664,17 +659,6 @@ > #define CURSOR_WIDTH 64 > #define CURSOR_HEIGHT 64 > > -#define AVIVO_D1VGA_CONTROL 0x00cc > -# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1 << 0) > -# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1 << 8) > -# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9) > -# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10) > -# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16) > -# define AVIVO_DVGA_CONTROL_ROTATE (1 << 24) > -#define AVIVO_D2VGA_CONTROL 0x00ce > - > -#define R600_BUS_CNTL 0x1508 > -# define R600_BIOS_ROM_DIS (1 << 1) > > #define R600_ROM_CNTL 0x580 > # define R600_SCK_OVERWRITE (1 << 1) > -- > 2.49.0 >
