Apart from minor comment LGTM.  Also lets wait for Alex to review the series.
Reviewed-by: Sunil Khatri <[email protected]>

On 4/10/2025 4:59 PM, Arvind Yadav wrote:
This patch is load usermode queue based on FW support for gfx12.
CP Ucode FW Vesion: [PFP = 2840, ME = 2780, MEC = 2600, MES = 123]

Cc: Alex Deucher <[email protected]>
Cc: Christian Koenig <[email protected]>
Cc: Shashank Sharma <[email protected]>
Cc: Sunil Khatri <[email protected]>
Signed-off-by: Arvind Yadav <[email protected]>
---
  drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 15 ++++++++++++++-
  1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 3d87e445270e..c31c96fc13f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -69,6 +69,10 @@
  #define regCP_HQD_PERSISTENT_STATE_DEFAULT                                    
    0x0be05501
  #define regCP_HQD_IB_CONTROL_DEFAULT                                          
    0x00300000
+#define GFX12_ME_FW_MIN_VERSION 0x00000adc
Alignment issue here.
+#define GFX12_PFP_FW_MIN_VERSION                                               
0x00000b18
+#define GFX12_MEC_FW_MIN_VERSION                                               
0x00000bea
+#define GFX12_MES_FW_MIN_VERSION                                               
0x0000007b
MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin");
  MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin");
@@ -1383,6 +1387,15 @@ static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device 
*adev)
        }
  }
+static bool gfx_v12_0_is_userq_supported(struct amdgpu_device *adev)
+{
+       return (adev->gfx.me_fw_version >= GFX12_ME_FW_MIN_VERSION &&
+               adev->gfx.pfp_fw_version >= GFX12_PFP_FW_MIN_VERSION &&
+               adev->gfx.mec_fw_version >= GFX12_MEC_FW_MIN_VERSION &&
+               adev->mes.fw_version[0] >= GFX12_MES_FW_MIN_VERSION);
+}
+
+
an extra empty line not needed here.
  static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
  {
        int i, j, k, r, ring_id = 0;
@@ -1418,7 +1431,7 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block 
*ip_block)
        case IP_VERSION(12, 0, 1):
  #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
                /* add firmware version checks here */
-               if (0) {
+               if (gfx_v12_0_is_userq_supported(adev)) {
                        adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
                        adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = 
&userq_mes_funcs;
                }

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