ping on this series? Alex
On Thu, Mar 20, 2025 at 12:57 PM Alex Deucher <[email protected]> wrote: > > In dev core dump, dump the full header fifo for > each queue. Each FIFO has 8 entries. > > Signed-off-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 62 +++++++++++++++++++++------ > 1 file changed, 49 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index f4dfa1418b740..64342160ff7d0 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -225,17 +225,36 @@ static const struct amdgpu_hwip_reg_entry > gc_reg_list_9[] = { > SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE), > SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT), > SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6), > - /* cp header registers */ > - SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), > - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), > - SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP), > - SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), > - SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), > /* SE status registers */ > SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0), > SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1), > SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2), > - SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3) > + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3), > + /* packet headers */ > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP) > }; > > static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = { > @@ -277,6 +296,14 @@ static const struct amdgpu_hwip_reg_entry > gc_cp_reg_list_9[] = { > SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO), > SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI), > SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP) > }; > > enum ta_ras_gfx_subblock { > @@ -7340,9 +7367,14 @@ static void gfx_v9_ip_print(struct amdgpu_ip_block > *ip_block, struct drm_printer > for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; > k++) { > drm_printf(p, "\nmec %d, pipe %d, queue > %d\n", i, j, k); > for (reg = 0; reg < reg_count; reg++) { > - drm_printf(p, "%-50s \t 0x%08x\n", > - > gc_cp_reg_list_9[reg].reg_name, > - > adev->gfx.ip_dump_compute_queues[index + reg]); > + if (i && > gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP) > + drm_printf(p, "%-50s \t > 0x%08x\n", > + > "mmCP_MEC_ME2_HEADER_DUMP", > + > adev->gfx.ip_dump_compute_queues[index + reg]); > + else > + drm_printf(p, "%-50s \t > 0x%08x\n", > + > gc_cp_reg_list_9[reg].reg_name, > + > adev->gfx.ip_dump_compute_queues[index + reg]); > } > index += reg_count; > } > @@ -7379,9 +7411,13 @@ static void gfx_v9_ip_dump(struct amdgpu_ip_block > *ip_block) > soc15_grbm_select(adev, 1 + i, j, k, 0, 0); > > for (reg = 0; reg < reg_count; reg++) { > - > adev->gfx.ip_dump_compute_queues[index + reg] = > - RREG32(SOC15_REG_ENTRY_OFFSET( > - > gc_cp_reg_list_9[reg])); > + if (i && > gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP) > + > adev->gfx.ip_dump_compute_queues[index + reg] = > + > RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP)); > + else > + > adev->gfx.ip_dump_compute_queues[index + reg] = > + > RREG32(SOC15_REG_ENTRY_OFFSET( > + > gc_cp_reg_list_9[reg])); > } > index += reg_count; > } > -- > 2.49.0 >
