[AMD Official Use Only - AMD Internal Distribution Only] Should the SDMA mask be ASIC specific ? I think some ASIC might need to be set to 0x3fc .
Shaoyun.liu -----Original Message----- From: amd-gfx <[email protected]> On Behalf Of Alex Deucher Sent: Thursday, March 20, 2025 10:23 AM To: [email protected] Cc: Deucher, Alexander <[email protected]>; Liang, Prike <[email protected]> Subject: [PATCH 2/3] drm/amdgpu/mes: clean up SDMA HQD loop Follow the same logic as the other IP types. Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index fddec5d1f2444..016af4e9c35fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -136,11 +136,9 @@ int amdgpu_mes_init(struct amdgpu_device *adev) } for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) { - /* zero sdma_hqd_mask for non-existent engine */ - if (adev->sdma.num_instances == 1) - adev->mes.sdma_hqd_mask[i] = i ? 0 : 0xfc; - else - adev->mes.sdma_hqd_mask[i] = 0xfc; + if (i >= adev->sdma.num_instances) + break; + adev->mes.sdma_hqd_mask[i] = 0xfc; } for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { -- 2.49.0
