On Mon, Dec 16, 2024 at 4:43 PM Elena Sakhnovitch <[email protected]> wrote: > > From: Elena Sakhnovitch <[email protected]> > > CP_IQ_WAIT_TIME2.QUE_SLEEP hardware default is 0x40, i.e. > 64, so we put the queue to sleep for 64,000 clock cycles. > This is too long, and setting it to 0x1 shoul be enough to > load date out of memory during queue connect. > Signed-off-by: Elena Sakhnovitch <[email protected]> > --- > drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h | 2 +- > drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h | 2 +- > drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h | 2 +-
These headers correspond to the hw powerup defaults. If you change them, that changes the semantic meaning of these headers. If you want to change the settings, it would be better to change the driver code that programs these registers. Alex > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h > index 320e1ee5df1a..da6762309c3c 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h > @@ -2479,7 +2479,7 @@ > #define mmCP_CONTEXT_CNTL_DEFAULT > 0x00750075 > #define mmCP_MAX_CONTEXT_DEFAULT > 0x00000007 > #define mmCP_IQ_WAIT_TIME1_DEFAULT > 0x40404040 > -#define mmCP_IQ_WAIT_TIME2_DEFAULT > 0x40404040 > +#define mmCP_IQ_WAIT_TIME2_DEFAULT > 0x10404040 > #define mmCP_RB0_BASE_HI_DEFAULT > 0x00000000 > #define mmCP_RB1_BASE_HI_DEFAULT > 0x00000000 > #define mmCP_VMID_RESET_DEFAULT > 0x00000000 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h > index 21d2f7d1debc..07b112b11a3f 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h > @@ -2320,7 +2320,7 @@ > #define mmCP_CONTEXT_CNTL_DEFAULT > 0x00750075 > #define mmCP_MAX_CONTEXT_DEFAULT > 0x00000007 > #define mmCP_IQ_WAIT_TIME1_DEFAULT > 0x40404040 > -#define mmCP_IQ_WAIT_TIME2_DEFAULT > 0x40404040 > +#define mmCP_IQ_WAIT_TIME2_DEFAULT > 0x10404040 > #define mmCP_RB0_BASE_HI_DEFAULT > 0x00000000 > #define mmCP_RB1_BASE_HI_DEFAULT > 0x00000000 > #define mmCP_VMID_RESET_DEFAULT > 0x00000000 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h > index 5bf84c6d0ec3..64183c888fd4 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h > @@ -1295,7 +1295,7 @@ > #define mmCP_CONTEXT_CNTL_DEFAULT > 0x00750075 > #define mmCP_MAX_CONTEXT_DEFAULT > 0x00000007 > #define mmCP_IQ_WAIT_TIME1_DEFAULT > 0x40404040 > -#define mmCP_IQ_WAIT_TIME2_DEFAULT > 0x40404040 > +#define mmCP_IQ_WAIT_TIME2_DEFAULT > 0x10404040 > #define mmCP_RB0_BASE_HI_DEFAULT > 0x00000000 > #define mmCP_RB1_BASE_HI_DEFAULT > 0x00000000 > #define mmCP_VMID_RESET_DEFAULT > 0x00000000 > -- > 2.34.1 >
