add guard band interface on smu v14.0.2/3

Signed-off-by: Kenneth Feng <[email protected]>
---
 .../gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
 drivers/gpu/drm/amd/pm/amdgpu_dpm.c           | 19 +++++++++++++++++++
 drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h       |  3 +++
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c     | 13 +++++++++++++
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  2 ++
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |  3 ++-
 .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c  | 10 ++++++++++
 7 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 19a48d98830a..c1dfde17d48f 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -388,6 +388,7 @@ struct amd_pm_funcs {
        int (*set_pp_table)(void *handle, const char *buf, size_t size);
        void (*debugfs_print_current_performance_level)(void *handle, struct 
seq_file *m);
        int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE 
type, bool en);
+       int (*add_guard_band)(void *handle, uint32_t gfx_gb, uint32_t soc_gb);
 /* export to amdgpu */
        struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
        int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 9dc82f4d7c93..30f09e4db46a 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -340,6 +340,25 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device 
*adev,
        return ret;
 }
 
+int amdgpu_dpm_add_gb(struct amdgpu_device *adev,
+                                   uint32_t gfx_gb, uint32_t soc_gb)
+{
+       const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+       int ret = 0;
+
+       if (amdgpu_sriov_vf(adev))
+               return 0;
+
+       if (pp_funcs && pp_funcs->add_guard_band) {
+               mutex_lock(&adev->pm.mutex);
+               ret = pp_funcs->add_guard_band(
+                       adev->powerplay.pp_handle, gfx_gb, soc_gb);
+               mutex_unlock(&adev->pm.mutex);
+       }
+
+       return ret;
+}
+
 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
                               uint32_t pstate)
 {
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index f5bf41f21c41..804bdc39d855 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -406,6 +406,9 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device 
*adev,
                                    enum PP_SMC_POWER_PROFILE type,
                                    bool en);
 
+int amdgpu_dpm_add_gb(struct amdgpu_device *adev,
+                                   uint32_t gfx_gb, uint32_t soc_gb);
+
 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev);
 
 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 9d7454b3c314..8795d5b9bfe3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2350,6 +2350,18 @@ static int smu_switch_power_profile(void *handle,
        return 0;
 }
 
+static int smu_add_guard_band(void* handle, uint32_t gfx_gb,
+                                                         uint32_t soc_gb)
+{
+       struct smu_context *smu = handle;
+
+       if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
+               !smu->ppt_funcs->add_gb)
+               return -EOPNOTSUPP;
+
+       return smu->ppt_funcs->add_gb(smu, gfx_gb, soc_gb);
+}
+
 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
 {
        struct smu_context *smu = handle;
@@ -3637,6 +3649,7 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
        .get_pp_table            = smu_sys_get_pp_table,
        .set_pp_table            = smu_sys_set_pp_table,
        .switch_power_profile    = smu_switch_power_profile,
+       .add_guard_band    = smu_add_guard_band,
        /* export to amdgpu */
        .dispatch_tasks          = smu_handle_dpm_task,
        .load_firmware           = smu_load_microcode,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index b44a185d07e8..032f99c64a16 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1440,6 +1440,8 @@ struct pptable_funcs {
         */
        int (*set_wbrf_exclusion_ranges)(struct smu_context *smu,
                                        struct freq_band_range 
*exclusion_ranges);
+       int (*add_gb)(struct smu_context *smu, uint32_t gfx_gb,
+                                       uint32_t soc_gb);
 };
 
 typedef enum {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index 12a7b0634ed5..74709e2da853 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -275,7 +275,8 @@
        __SMU_DUMMY_MAP(RmaDueToBadPageThreshold),\
        __SMU_DUMMY_MAP(SelectPstatePolicy), \
        __SMU_DUMMY_MAP(MALLPowerController), \
-       __SMU_DUMMY_MAP(MALLPowerState),
+       __SMU_DUMMY_MAP(MALLPowerState), \
+       __SMU_DUMMY_MAP(UpdatePolicy),
 
 #undef __SMU_DUMMY_MAP
 #define __SMU_DUMMY_MAP(type)  SMU_MSG_##type
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index e000ac7b4c0e..40ea4c1d044f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
@@ -135,6 +135,7 @@ static struct cmn2asic_msg_mapping 
smu_v14_0_2_message_map[SMU_MSG_MAX_COUNT] =
                            PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel,  
 0),
        MSG_MAP(AllowIHHostInterrupt,           PPSMC_MSG_AllowIHHostInterrupt, 
      0),
        MSG_MAP(ReenableAcDcInterrupt,          
PPSMC_MSG_ReenableAcDcInterrupt,       0),
+       MSG_MAP(UpdatePolicy,           PPSMC_MSG_UpdatePolicy,       0),
 };
 
 static struct cmn2asic_mapping smu_v14_0_2_clk_map[SMU_CLK_COUNT] = {
@@ -2828,6 +2829,14 @@ static int smu_v14_0_2_set_power_limit(struct 
smu_context *smu,
        return 0;
 }
 
+static int smu_v14_0_2_add_gb(struct smu_context* smu, uint32_t gfx_gb,
+                                                         uint32_t soc_gb) {
+       uint32_t param = (gfx_gb & 0xF) << 16 | (soc_gb & 0xF);
+
+       return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_UpdatePolicy,
+                                         param, NULL);
+}
+
 static const struct pptable_funcs smu_v14_0_2_ppt_funcs = {
        .get_allowed_feature_mask = smu_v14_0_2_get_allowed_feature_mask,
        .set_default_dpm_table = smu_v14_0_2_set_default_dpm_table,
@@ -2902,6 +2911,7 @@ static const struct pptable_funcs smu_v14_0_2_ppt_funcs = 
{
        .gpo_control = smu_v14_0_gpo_control,
 #endif
        .get_ecc_info = smu_v14_0_2_get_ecc_info,
+       .add_gb = smu_v14_0_2_add_gb,
 };
 
 void smu_v14_0_2_set_ppt_funcs(struct smu_context *smu)
-- 
2.34.1

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