Add missing register programming for mcache in DCN401.
Reviewed-by: Aurabindo Pillai <[email protected]>
Signed-off-by: Rodrigo Siqueira <[email protected]>
---
.../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
index 106008593464..514d1ce20df9 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
@@ -138,7 +138,9 @@ void dcn401_prepare_mcache_programming(struct dc *dc,
struct dc_state *context);
SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id),
\
SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id),
\
SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id),
\
- HUBP_3DLUT_FL_REG_LIST_DCN401(id)
+ HUBP_3DLUT_FL_REG_LIST_DCN401(id),
\
+ SRI_ARR(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, HUBP, id),
\
+ SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id)
/* ABM */
#define ABM_DCN401_REG_LIST_RI(id) \
--
2.43.0
