On Tue, Nov 21, 2023 at 4:27 AM Li Ma <[email protected]> wrote: > > enable init_registers callback func for nbio v7.11. > > Signed-off-by: Li Ma <[email protected]>
Acked-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c | 18 ++++++------ > .../asic_reg/nbio/nbio_7_11_0_offset.h | 2 ++ > .../asic_reg/nbio/nbio_7_11_0_sh_mask.h | 29 +++++++++++++++++++ > 3 files changed, 40 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c > b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c > index 676ab1d20d2f..1f52b4b1db03 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c > +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c > @@ -259,17 +259,17 @@ const struct nbio_hdp_flush_reg > nbio_v7_11_hdp_flush_reg = { > > static void nbio_v7_11_init_registers(struct amdgpu_device *adev) > { > -/* uint32_t def, data; > + uint32_t def, data; > + > + def = data = RREG32_SOC15(NBIO, 0, > regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3); > + data = REG_SET_FIELD(data, > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, > + CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); > + data = REG_SET_FIELD(data, > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, > + CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); > > - def = data = RREG32_SOC15(NBIO, 0, > regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3); > - data = REG_SET_FIELD(data, > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, > - CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); > - data = REG_SET_FIELD(data, > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, > - CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); > + if (def != data) > + WREG32_SOC15(NBIO, 0, > regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data); > > - if (def != data) > - WREG32_SOC15(NBIO, 0, > regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data); > -*/ > } > > static void nbio_v7_11_update_medium_grain_clock_gating(struct amdgpu_device > *adev, > diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h > b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h > index ff30f04be591..7ee3d291120d 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h > @@ -781,6 +781,8 @@ > #define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2_BASE_IDX > 5 > #define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1 > 0x420187 > #define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1_BASE_IDX > 5 > +#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3 > 0x4201c6 > +#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3_BASE_IDX > 5 > > > // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp > diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h > b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h > index 7f131999a263..eb8c556d9c93 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h > @@ -24646,6 +24646,35 @@ > //BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1 > #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK > 0x00000001L > #define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK > 0x00000008L > +//BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3 > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT > 0x8 > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT > 0x9 > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_10BIT_TAG_EN_OVERRIDE__SHIFT > 0xb > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_10BIT_TAG_EN_OVERRIDE__SHIFT > 0xd > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__MST_DROP_SYNC_FLOOD_EN__SHIFT > 0xf > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT > 0x10 > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT > 0x11 > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT > 0x14 > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT > 0x15 > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_SAFE_MODE__SHIFT > 0x18 > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT > 0x19 > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT > 0x1b > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT > 0x1c > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT > 0x1e > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK > 0x00000100L > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK > 0x00000600L > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_10BIT_TAG_EN_OVERRIDE_MASK > 0x00001800L > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_10BIT_TAG_EN_OVERRIDE_MASK > 0x00006000L > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__MST_DROP_SYNC_FLOOD_EN_MASK > 0x00008000L > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_PAYLOAD_SIZE_MODE_MASK > 0x00010000L > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_PAYLOAD_SIZE_MASK > 0x000E0000L > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_REQUEST_SIZE_MODE_MASK > 0x00100000L > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK > 0x00E00000L > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_SAFE_MODE_MASK > 0x01000000L > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_EXTENDED_TAG_EN_OVERRIDE_MASK > 0x06000000L > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK > 0x08000000L > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK > 0x30000000L > +#define > BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK > 0xC0000000L > > // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp > //BIF_CFG_DEV0_RC0_VENDOR_ID > -- > 2.25.1 >
