[PATCH v2 07/21] drm/amdgpu: abstract disable identity aperture for gfxhub/mmhub

[Huang Rui]

Signed-off-by: Huang Rui <ray.hu...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 37 ++++++++++++++++++--------------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 36 +++++++++++++++++--------------
 2 files changed, 41 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 495718d..ab77a57 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -170,6 +170,26 @@ static void gfxhub_v1_0_enable_system_domain(struct 
amdgpu_device *adev)
        WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);
 }
 
+static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
+{
+       WREG32(SOC15_REG_OFFSET(GC, 0,
+                               
mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
+              0XFFFFFFFF);
+       WREG32(SOC15_REG_OFFSET(GC, 0,
+               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
+
+       WREG32(SOC15_REG_OFFSET(GC, 0,
+               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
+       WREG32(SOC15_REG_OFFSET(GC, 0,
+               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
+
+       WREG32(SOC15_REG_OFFSET(GC, 0,
+               mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
+       WREG32(SOC15_REG_OFFSET(GC, 0,
+               mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
+
+}
+
 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
        u32 tmp;
@@ -195,22 +215,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
        gfxhub_v1_0_init_cache_regs(adev);
 
        gfxhub_v1_0_enable_system_domain(adev);
-
-       /* Disable identity aperture.*/
-       WREG32(SOC15_REG_OFFSET(GC, 0,
-               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);
-       WREG32(SOC15_REG_OFFSET(GC, 0,
-               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
-
-       WREG32(SOC15_REG_OFFSET(GC, 0,
-               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
-       WREG32(SOC15_REG_OFFSET(GC, 0,
-               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
-
-       WREG32(SOC15_REG_OFFSET(GC, 0,
-               mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
-       WREG32(SOC15_REG_OFFSET(GC, 0,
-               mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
+       gfxhub_v1_0_disable_identity_aperture(adev);
 
        for (i = 0; i <= 14; i++) {
                tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index dc7e3bd..b64a7cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -183,6 +183,25 @@ static void mmhub_v1_0_enable_system_domain(struct 
amdgpu_device *adev)
        WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp);
 }
 
+static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
+{
+       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+                               
mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
+              0XFFFFFFFF);
+       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
+
+       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
+       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
+
+       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+               mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
+       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+               mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
+}
+
 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
        u32 tmp;
@@ -208,22 +227,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
        mmhub_v1_0_init_cache_regs(adev);
 
        mmhub_v1_0_enable_system_domain(adev);
-
-       /* Disable identity aperture.*/
-       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);
-       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
-
-       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
-       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-               mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
-
-       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-               mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
-       WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-               mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
+       mmhub_v1_0_disable_identity_aperture(adev);
 
        for (i = 0; i <= 14; i++) {
                tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL)
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx