For SRIOV, multi vce engine will hang when encoding. Add VMHUB flush to workaround it, will continue to find the root cause later.
Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Frank Min <[email protected]> --- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index d3448d0..b4e36f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -31,6 +31,7 @@ #include "soc15d.h" #include "soc15_common.h" #include "mmsch_v1_0.h" +#include "gmc_v9_0.h" #include "vega10/soc15ip.h" #include "vega10/VCE/vce_4_0_offset.h" @@ -971,6 +972,7 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring, uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); unsigned eng = ring->idx; unsigned i; + struct amdgpu_device *adev = ring->adev; pd_addr = pd_addr | 0x1; /* valid bit */ /* now only use physical base address of PDE and valid */ @@ -979,6 +981,15 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring, for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { struct amdgpu_vmhub *hub = &ring->adev->vmhub[i]; + /* Workaround multi vce engine encoding hang issue */ + if (i && amdgpu_sriov_vf(adev)) { + WREG32_NO_KIQ(hub->ctx0_ptb_addr_lo32 + vm_id * 2, + lower_32_bits(pd_addr)); + WREG32_NO_KIQ(hub->ctx0_ptb_addr_hi32 + vm_id * 2, + upper_32_bits(pd_addr)); + gmc_v9_0_flush_vmhub(adev, hub, eng, vm_id); + } + amdgpu_ring_write(ring, VCE_CMD_REG_WRITE); amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2); -- 2.7.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
