Because in the first place we have no reason to use delay work, We use delay work in staging branch is because Xiangliang's TDR/RESET feature is separated into two steps: part A and part B, Part B must begin after part A, so Xiangliang use delay work to schedule part B, (and this design has a negative side is that if part A not finished yet, running part B may not good, so I dropped this design and come up with the one you are reviewing now)
But my TDR feature is overall one together, so no need to use delay work at all BR Monk -----Original Message----- From: Deucher, Alexander Sent: Wednesday, February 08, 2017 12:11 AM To: Liu, Monk <[email protected]>; [email protected] Cc: Liu, Monk <[email protected]> Subject: RE: [PATCH 15/20] drm/amdgpu:use work instead of delay-work > -----Original Message----- > From: amd-gfx [mailto:[email protected]] On Behalf > Of Monk Liu > Sent: Tuesday, February 07, 2017 1:11 AM > To: [email protected] > Cc: Liu, Monk > Subject: [PATCH 15/20] drm/amdgpu:use work instead of delay-work > > Change-Id: I41b6336baa00b1fd299311349402a17951b585a2 > Signed-off-by: Monk Liu <[email protected]> Please add a better patch description. Why is this change needed? > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 +- > drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 36 +++++++++++++++-------- > --------- > 2 files changed, 18 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h > index 4b05568..846f29c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h > @@ -50,7 +50,7 @@ struct amdgpu_virt { > struct mutex lock_reset; > struct amdgpu_irq_src ack_irq; > struct amdgpu_irq_src rcv_irq; > - struct delayed_work flr_work; > + struct work_struct flr_work; > const struct amdgpu_virt_ops *ops; > }; > > diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c > b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c > index 4e9e0bb..53fa590c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c > +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c > @@ -503,17 +503,19 @@ static int xgpu_vi_set_mailbox_ack_irq(struct > amdgpu_device *adev, > > static void xgpu_vi_mailbox_flr_work(struct work_struct *work) { > - struct amdgpu_virt *virt = container_of(work, > - struct amdgpu_virt, flr_work.work); > - struct amdgpu_device *adev = container_of(virt, > - struct amdgpu_device, virt); > - int r = 0; > - > - r = xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL); > - if (r) > - DRM_ERROR("failed to get flr cmpl msg from hypervior.\n"); > + struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, > flr_work); > + struct amdgpu_device *adev = container_of(virt, struct > amdgpu_device, virt); > + > + /* wait until RCV_MSG become 3 */ > + if (!xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) > + adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; > + else { > + pr_err("failed to recieve FLR_CMPL\n"); > + return; > + } > > - /* TODO: need to restore gfx states */ > + /* Trigger recovery due to world switch failure */ > + amdgpu_sriov_gpu_reset(adev, false); > } > > static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev, @@ > -536,15 +538,12 @@ static int xgpu_vi_mailbox_rcv_irq(struct > amdgpu_device *adev, { > int r; > > - adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; > + /* see what event we get */ > r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION); > - /* do nothing for other msg */ > - if (r) > - return 0; > > - /* TODO: need to save gfx states */ > - schedule_delayed_work(&adev->virt.flr_work, > - msecs_to_jiffies(VI_MAILBOX_RESET_TIME)); > + /* only handle FLR_NOTIFY now */ > + if (!r) > + schedule_work(&adev->virt.flr_work); > > return 0; > } > @@ -597,14 +596,13 @@ int xgpu_vi_mailbox_get_irq(struct amdgpu_device > *adev) > return r; > } > > - INIT_DELAYED_WORK(&adev->virt.flr_work, > xgpu_vi_mailbox_flr_work); > + INIT_WORK(&adev->virt.flr_work, xgpu_vi_mailbox_flr_work); > > return 0; > } > > void xgpu_vi_mailbox_put_irq(struct amdgpu_device *adev) { > - cancel_delayed_work_sync(&adev->virt.flr_work); > amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); > amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); } > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
