> -----Original Message-----
> From: amd-gfx [mailto:[email protected]] On Behalf
> Of Michel Dänzer
> Sent: Tuesday, November 08, 2016 4:37 AM
> To: Christian König
> Cc: [email protected]
> Subject: Re: [PATCH 1/2] drm/amdgpu: access stolen VRAM directly on
> KV/KB
> 
> On 08/11/16 06:23 PM, Christian König wrote:
> > Am 08.11.2016 um 08:31 schrieb Michel Dänzer:
> >> On 07/11/16 06:33 PM, Christian König wrote:
> >>> Am 07.11.2016 um 10:29 schrieb Michel Dänzer:
> >>>> On 07/11/16 06:21 PM, Christian König wrote:
> >>>>> From: Christian König <[email protected]>
> >>>>>
> >>>>> We don't need to use the PCI BAR on APUs. This allows us to access
> >>>>> the full VRAM directly without being limited by the BAR size.
> >>>>>
> >>>>> Signed-off-by: Christian König <[email protected]>
> >>>> The series is
> >>>>
> >>>> Reviewed-by: Michel Dänzer <[email protected]>
> >>>>
> >>>>
> >>>> We could also drop the HDP flushes / invalidates in this case, right?
> >>> Could be, but I'm not 100% sure how those are actually wired up on
> APUs.
> >>>
> >>> Might be that they are NOPs anyway, but could be that at least the
> >>> flushes are still vital.
> >> My assumption is that since CPU access to VRAM doesn't go through the
> >> HDP at all with this change, HDP flushes / invalidates can't have any
> >> useful effect.
> >
> > Well writes to GTT still use the HDP if I understand it correctly.
> >
> > So we still need to handle either flushes or invalidations (I doesn't of
> > hand remember which was that).
> 
> Do you mean GPU access to GTT? If so, not sure why it would be writes only?

The HDP has a read cache and a write queue.  It only affects access via the BAR 
(either the CPU or another PCIe device).  AFAIK, the APU access would only use 
the HDP if you mapped the BAR via the GART.

Alex

> 
> 
> --
> Earthling Michel Dänzer               |               http://www.amd.com
> Libre software enthusiast             |             Mesa and X developer
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