On Mon, Sep 19, 2016 at 1:45 PM, Tom St Denis <[email protected]> wrote: > Replace per-asic print_current_performance() functions with generic > that calls read_sensor. Tested on Tonga and Carrizo for aesthetics > and accuracy. > > Signed-off-by: Tom St Denis <[email protected]>
Reviewed-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 +-- > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 62 +++++++++++++++++- > drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 23 ------- > drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 79 > ++--------------------- > drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 39 ++--------- > drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 4 +- > drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 - > 7 files changed, 79 insertions(+), 140 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index f93c1868d31d..d39fb1ac0c0a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -2352,6 +2352,11 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) > #define amdgpu_gfx_get_gpu_clock_counter(adev) > (adev)->gfx.funcs->get_gpu_clock_counter((adev)) > #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) > (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) > > +#define amdgpu_dpm_read_sensor(adev, idx, value) \ > + ((adev)->pp_enabled ? \ > + > (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), > (value)) : \ > + -EINVAL) > + > #define amdgpu_dpm_get_temperature(adev) \ > ((adev)->pp_enabled ? \ > > (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ > @@ -2403,11 +2408,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) > > (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : > \ > (adev)->pm.funcs->powergate_vce((adev), (g))) > > -#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ > - ((adev)->pp_enabled ? \ > - > (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, > (m)) : \ > - > (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))) > - > #define amdgpu_dpm_get_current_power_state(adev) \ > > (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c > index cded0820dc59..5307107d76ea 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c > @@ -1321,6 +1321,64 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device > *adev) > */ > #if defined(CONFIG_DEBUG_FS) > > +static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct > amdgpu_device *adev) > +{ > + int32_t value; > + > + /* sanity check PP is enabled */ > + if (!(adev->powerplay.pp_funcs && > + adev->powerplay.pp_funcs->read_sensor)) > + return -EINVAL; > + > + /* GPU Clocks */ > + seq_printf(m, "GFX Clocks and Power:\n"); > + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, &value)) > + seq_printf(m, "\t%u MHz (MCLK)\n", value/100); > + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, &value)) > + seq_printf(m, "\t%u MHz (SCLK)\n", value/100); > + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, &value)) > + seq_printf(m, "\t%u mV (VDDGFX)\n", value); > + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, &value)) > + seq_printf(m, "\t%u mV (VDDNB)\n", value); > + seq_printf(m, "\n"); > + > + /* GPU Temp */ > + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, &value)) > + seq_printf(m, "GPU Temperature: %u C\n", value/1000); > + > + /* GPU Load */ > + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value)) > + seq_printf(m, "GPU Load: %u %%\n", value); > + seq_printf(m, "\n"); > + > + /* UVD clocks */ > + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, > &value)) { > + if (!value) { > + seq_printf(m, "UVD: Disabled\n"); > + } else { > + seq_printf(m, "UVD: Enabled\n"); > + if (!amdgpu_dpm_read_sensor(adev, > AMDGPU_PP_SENSOR_UVD_DCLK, &value)) > + seq_printf(m, "\t%u MHz (DCLK)\n", value/100); > + if (!amdgpu_dpm_read_sensor(adev, > AMDGPU_PP_SENSOR_UVD_VCLK, &value)) > + seq_printf(m, "\t%u MHz (VCLK)\n", value/100); > + } > + } > + seq_printf(m, "\n"); > + > + /* VCE clocks */ > + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, > &value)) { > + if (!value) { > + seq_printf(m, "VCE: Disabled\n"); > + } else { > + seq_printf(m, "VCE: Enabled\n"); > + if (!amdgpu_dpm_read_sensor(adev, > AMDGPU_PP_SENSOR_VCE_ECCLK, &value)) > + seq_printf(m, "\t%u MHz (ECCLK)\n", > value/100); > + } > + } > + > + return 0; > +} > + > static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) > { > struct drm_info_node *node = (struct drm_info_node *) m->private; > @@ -1336,11 +1394,11 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, > void *data) > (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { > seq_printf(m, "PX asic powered off\n"); > } else if (adev->pp_enabled) { > - amdgpu_dpm_debugfs_print_current_performance_level(adev, m); > + return amdgpu_debugfs_pm_info_pp(m, adev); > } else { > mutex_lock(&adev->pm.mutex); > if (adev->pm.funcs->debugfs_print_current_performance_level) > - > amdgpu_dpm_debugfs_print_current_performance_level(adev, m); > + > adev->pm.funcs->debugfs_print_current_performance_level(adev, m); > else > seq_printf(m, "Debugfs support not implemented for > this asic\n"); > mutex_unlock(&adev->pm.mutex); > diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > index ee0368381e82..212ec2fd97ed 100644 > --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > @@ -576,28 +576,6 @@ enum amd_pm_state_type > pp_dpm_get_current_power_state(void *handle) > } > } > > -static void > -pp_debugfs_print_current_performance_level(void *handle, > - struct seq_file *m) > -{ > - struct pp_hwmgr *hwmgr; > - > - if (handle == NULL) > - return; > - > - hwmgr = ((struct pp_instance *)handle)->hwmgr; > - > - if (hwmgr == NULL || hwmgr->hwmgr_func == NULL) > - return; > - > - if (hwmgr->hwmgr_func->print_current_perforce_level == NULL) { > - printk(KERN_INFO "%s was not implemented.\n", __func__); > - return; > - } > - > - hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m); > -} > - > static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) > { > struct pp_hwmgr *hwmgr; > @@ -925,7 +903,6 @@ const struct amd_powerplay_funcs pp_dpm_funcs = { > .powergate_vce = pp_dpm_powergate_vce, > .powergate_uvd = pp_dpm_powergate_uvd, > .dispatch_tasks = pp_dpm_dispatch_tasks, > - .print_current_performance_level = > pp_debugfs_print_current_performance_level, > .set_fan_control_mode = pp_dpm_set_fan_control_mode, > .get_fan_control_mode = pp_dpm_get_fan_control_mode, > .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c > index 9f3c5a8a903c..7e4fcbbbe086 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c > @@ -1538,78 +1538,6 @@ int cz_get_power_state_size(struct pp_hwmgr *hwmgr) > return sizeof(struct cz_power_state); > } > > -static void > -cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m) > -{ > - struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); > - > - struct phm_clock_voltage_dependency_table *table = > - hwmgr->dyn_state.vddc_dependency_on_sclk; > - > - struct phm_vce_clock_voltage_dependency_table *vce_table = > - hwmgr->dyn_state.vce_clock_voltage_dependency_table; > - > - struct phm_uvd_clock_voltage_dependency_table *uvd_table = > - hwmgr->dyn_state.uvd_clock_voltage_dependency_table; > - > - uint32_t sclk_index = > PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, > ixTARGET_AND_CURRENT_PROFILE_INDEX), > - TARGET_AND_CURRENT_PROFILE_INDEX, > CURR_SCLK_INDEX); > - uint32_t uvd_index = > PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, > ixTARGET_AND_CURRENT_PROFILE_INDEX_2), > - TARGET_AND_CURRENT_PROFILE_INDEX_2, > CURR_UVD_INDEX); > - uint32_t vce_index = > PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, > ixTARGET_AND_CURRENT_PROFILE_INDEX_2), > - TARGET_AND_CURRENT_PROFILE_INDEX_2, > CURR_VCE_INDEX); > - > - uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; > - uint16_t vddnb, vddgfx; > - int result; > - > - if (sclk_index >= NUM_SCLK_LEVELS) { > - seq_printf(m, "\n invalid sclk dpm profile %d\n", sclk_index); > - } else { > - sclk = table->entries[sclk_index].clk; > - seq_printf(m, "\n index: %u sclk: %u MHz\n", sclk_index, > sclk/100); > - } > - > - tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, > ixSMUSVI_NB_CURRENTVID) & > - CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT; > - vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp); > - tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, > ixSMUSVI_GFX_CURRENTVID) & > - CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT; > - vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp); > - seq_printf(m, "\n vddnb: %u vddgfx: %u\n", vddnb, vddgfx); > - > - seq_printf(m, "\n uvd %sabled\n", cz_hwmgr->uvd_power_gated ? > "dis" : "en"); > - if (!cz_hwmgr->uvd_power_gated) { > - if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) { > - seq_printf(m, "\n invalid uvd dpm level %d\n", > uvd_index); > - } else { > - vclk = uvd_table->entries[uvd_index].vclk; > - dclk = uvd_table->entries[uvd_index].dclk; > - seq_printf(m, "\n index: %u uvd vclk: %u MHz dclk: %u > MHz\n", uvd_index, vclk/100, dclk/100); > - } > - } > - > - seq_printf(m, "\n vce %sabled\n", cz_hwmgr->vce_power_gated ? > "dis" : "en"); > - if (!cz_hwmgr->vce_power_gated) { > - if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) { > - seq_printf(m, "\n invalid vce dpm level %d\n", > vce_index); > - } else { > - ecclk = vce_table->entries[vce_index].ecclk; > - seq_printf(m, "\n index: %u vce ecclk: %u MHz\n", > vce_index, ecclk/100); > - } > - } > - > - result = smum_send_msg_to_smc(hwmgr->smumgr, > PPSMC_MSG_GetAverageGraphicsActivity); > - if (0 == result) { > - activity_percent = cgs_read_register(hwmgr->device, > mmSMU_MP1_SRBM2P_ARG_0); > - activity_percent = activity_percent > 100 ? 100 : > activity_percent; > - } else { > - activity_percent = 50; > - } > - > - seq_printf(m, "\n [GPU load]: %u %%\n\n", activity_percent); > -} > - > static void cz_hw_print_display_cfg( > const struct cc6_settings *cc6_settings) > { > @@ -1947,6 +1875,12 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int > idx, int32_t *value) > } > *value = activity_percent; > return 0; > + case AMDGPU_PP_SENSOR_UVD_POWER: > + *value = cz_hwmgr->uvd_power_gated ? 0 : 1; > + return 0; > + case AMDGPU_PP_SENSOR_VCE_POWER: > + *value = cz_hwmgr->vce_power_gated ? 0 : 1; > + return 0; > default: > return -EINVAL; > } > @@ -1967,7 +1901,6 @@ static const struct pp_hwmgr_func cz_hwmgr_funcs = { > .patch_boot_state = cz_dpm_patch_boot_state, > .get_pp_table_entry = cz_dpm_get_pp_table_entry, > .get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries, > - .print_current_perforce_level = cz_print_current_perforce_level, > .set_cpu_power_state = cz_set_cpu_power_state, > .store_cc6_data = cz_store_cc6_data, > .force_clock_level = cz_force_clock_level, > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > index 07a7d046d6f6..a3832f2d893b 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > @@ -3112,38 +3112,6 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr > *hwmgr, > return 0; > } > > -static void > -smu7_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m) > -{ > - uint32_t sclk, mclk, activity_percent; > - uint32_t offset; > - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); > - > - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); > - > - sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); > - > - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); > - > - mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); > - seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", > - mclk / 100, sclk / 100); > - > - offset = data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, > - SMU_SoftRegisters, > - > AverageGraphicsActivity); > - > - activity_percent = cgs_read_ind_register(hwmgr->device, > CGS_IND_REG__SMC, offset); > - activity_percent += 0x80; > - activity_percent >>= 8; > - > - seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 > : activity_percent); > - > - seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : > "en"); > - > - seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : > "en"); > -} > - > static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value) > { > uint32_t sclk, mclk, activity_percent; > @@ -3174,6 +3142,12 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, > int idx, int32_t *value) > case AMDGPU_PP_SENSOR_GPU_TEMP: > *value = smu7_thermal_get_temperature(hwmgr); > return 0; > + case AMDGPU_PP_SENSOR_UVD_POWER: > + *value = data->uvd_power_gated ? 0 : 1; > + return 0; > + case AMDGPU_PP_SENSOR_VCE_POWER: > + *value = data->vce_power_gated ? 0 : 1; > + return 0; > default: > return -EINVAL; > } > @@ -4318,7 +4292,6 @@ static struct pp_hwmgr_func smu7_hwmgr_funcs = { > .patch_boot_state = smu7_dpm_patch_boot_state, > .get_pp_table_entry = smu7_get_pp_table_entry, > .get_num_of_pp_table_entries = > smu7_get_number_of_powerplay_table_entries, > - .print_current_perforce_level = smu7_print_current_perforce_level, > .powerdown_uvd = smu7_powerdown_uvd, > .powergate_uvd = smu7_powergate_uvd, > .powergate_vce = smu7_powergate_vce, > diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h > b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h > index dfa0f38a5e76..3d74043c0e08 100644 > --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h > +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h > @@ -39,6 +39,8 @@ enum amd_pp_sensors { > AMDGPU_PP_SENSOR_GPU_LOAD, > AMDGPU_PP_SENSOR_GFX_MCLK, > AMDGPU_PP_SENSOR_GPU_TEMP, > + AMDGPU_PP_SENSOR_VCE_POWER, > + AMDGPU_PP_SENSOR_UVD_POWER, > }; > > enum amd_pp_event { > @@ -343,8 +345,6 @@ struct amd_powerplay_funcs { > int (*powergate_uvd)(void *handle, bool gate); > int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id, > void *input, void *output); > - void (*print_current_performance_level)(void *handle, > - struct seq_file *m); > int (*set_fan_control_mode)(void *handle, uint32_t mode); > int (*get_fan_control_mode)(void *handle); > int (*set_fan_speed_percent)(void *handle, uint32_t percent); > diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h > b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h > index fcd45452380d..4f0fedd1e9d3 100644 > --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h > +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h > @@ -311,8 +311,6 @@ struct pp_hwmgr_func { > int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low); > int (*power_state_set)(struct pp_hwmgr *hwmgr, > const void *state); > - void (*print_current_perforce_level)(struct pp_hwmgr *hwmgr, > - struct seq_file *m); > int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr); > int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr > *hwmgr); > int (*display_config_changed)(struct pp_hwmgr *hwmgr); > -- > 2.10.0 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
