Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
---
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 4 +---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 36 +++++++++++++++++++++-------
2 files changed, 28 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index 129c1d0..cbf0153 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -8,9 +8,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
process_pptables_v1_0.o ppatomctrl.o \
pppcielanes.o \
smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
- smu7_clockpowergating.o iceland_hwmgr.o \
- iceland_clockpowergating.o iceland_thermal.o \
- iceland_powertune.o
+ smu7_clockpowergating.o
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 11a4683..6354008 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -36,13 +36,13 @@
#include "amd_acpi.h"
extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
-extern int iceland_hwmgr_init(struct pp_hwmgr *hwmgr);
static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
+static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
uint8_t convert_to_vid(uint16_t vddc)
{
@@ -78,31 +78,33 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct
pp_instance *handle)
case AMDGPU_FAMILY_VI:
switch (hwmgr->chip_id) {
case CHIP_TOPAZ:
- iceland_hwmgr_init(hwmgr);
+ topaz_set_asic_special_caps(hwmgr);
+ hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK |
+ PP_VBI_TIME_SUPPORT_MASK |
+ PP_ULV_MASK |
+ PP_ENABLE_GFX_CG_THRU_SMU);
+ hwmgr->pp_table_version = PP_TABLE_V0;
break;
case CHIP_TONGA:
- smu7_hwmgr_init(hwmgr);
tonga_set_asic_special_caps(hwmgr);
hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK |
PP_VBI_TIME_SUPPORT_MASK |
PP_ULV_MASK);
break;
case CHIP_FIJI:
- smu7_hwmgr_init(hwmgr);
fiji_set_asic_special_caps(hwmgr);
hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK |
- PP_VBI_TIME_SUPPORT_MASK |
- PP_ENABLE_GFX_CG_THRU_SMU);
+ PP_VBI_TIME_SUPPORT_MASK);
break;
case CHIP_POLARIS11:
case CHIP_POLARIS10:
- smu7_hwmgr_init(hwmgr);
polaris_set_asic_special_caps(hwmgr);
hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
break;
default:
return -EINVAL;
}
+ smu7_hwmgr_init(hwmgr);
break;
default:
return -EINVAL;
@@ -215,8 +217,6 @@ int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t
index,
}
-
-
/**
* Returns once the part of the register indicated by the mask has
* reached the given value.The indirect space is described by giving
@@ -830,3 +830,21 @@ int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
return 0;
}
+
+int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
+{
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SQRamping);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_DBRamping);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_TDRamping);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_TCPRamping);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_CAC);
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_EVV);
+ return 0;
+}
--
1.9.1
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